here to go to our main page on semiconductor wafer processing
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here to go to our page on solid-state switches (for info on
here to go to our page on semiconductor technology tradeoffs
here to go to our page on curve tracer measurements
Welcome to the best web page
on microwave FETs! This tutorial will provide an “outstanding understanding”
of FETs as they are applied in microwave engineering; all of this
information is directly applicable to understanding monolithic microwave
integrated circuits (MMICs).
New for September 2012! Let's start this page off with some information on how the phase "drain bias" is often misused. We've been guilty of this ourselves but will work to clean up our act. Below an email from Chris is paraphrased:
Gates are "biased", as are grids and bases, but plates, collectors and drains are supplied with voltage. I think the (mis)use of the word "bias" has been started by non-native English speakers, who has no conception of the English word "bias". As we all know setting the quiescent current in an amplifying device (Idq for a FET) is set by the normal, no-signal, voltage (or current) of the control element ( grid, gate, base etc). If we set zero current thru the main current path, varying the voltage on the drain, or plate etc, will not change that current, unless you send it into breakdown, which would be a dumb idea. Thus the plate, drain etc. cannot be responsible for the device quiescent current, and cannot be called a "bias" terminal. For the drain terminal, "bias voltage" should perhaps be substituted with the words "supply voltage " or just "voltage".
"Drain bias" is a misnomer, and should be avoided as much as "tech", as it is factually incorrect.
Chris, now that you have explained this we completely agree, and will hunt down and remove all references to "drain bias" on the site. Thanks! - UE
We are putting this important
chapter of Microwaves101 onto the site in several installments because
this topic is so huge in microwave engineering. The first installment
is up and running as of Summer of 2003, and includes basic theory,
all the terminology you will ever need, how FETs are made, and a
discussion of I-V and transfer curves. Future installments will
describe bias networks, including self-biasing analysis, small-signal
equivalent-circuit modeling, FET power handling, and a large-signal
discussion including drain efficiency, power-added efficiency, and
load line analysis using the method first described by Steve Cripps
(he was the first person to note that the reactive part of a FET's
output equivalent circuit accurately describes its load pull contours).
It is truly amazing how many brilliant microwave guys are named
Steve. Contact us if there is any specific info we've omitted that
you'd like to see here!
Here is a clickable table of
contents for this page:
(includes terminology and answers to FAQs)
FETs are made (moved to a separate page)
and transfer curves
What’s a FET?
In microwaves we are almost always referring to a MESFET, which
stands for metal-semiconductor field effect transistor. A FET is
a three terminal device capable of both microwave amplification
and switching. The FET’s three terminals are denoted as gate, source
and drain. With respect to a bipolar transistor (BJT), the gate
of a FET corresponds to the base of a BJT, the drain corresponds
to the collector and the source corresponds to the emitter terminal.
This is useful knowledge since every curve
tracer we've ever seen in a lab has its three terminals labeled
collector, base, and emitter, not drain, gate, and source. Pay attention,
in case your boss puts you on the spot someday!
Used as an amplifier, the gate
is most often configured as the input terminal, the source is grounded
and the drain is the output. The output current (IDS) is controlled
by the input voltage (VGS). This configuration is called common
source since the source is common to the input and output ground
connections. It is also possible (but unusual) to ground the gate
and create a common-gate amplifier. Such an amplifier does not
provide the voltage gain of the common-source amplifier, but it
has the interesting property of being easier to impedance match
than a "normal" common-source amplifier. We won’t get
into that here.
figure below shows a cross-section of the channel of a field-effect
transistor and explains some FET terminology. The drain and source
are connected by the FET channel, which is formed by creating a
mesa of N-type semiconductor (for an N-channel FET) on top of a
semi-insulating substrate (typically GaAs). In microwaves we are
almost often dealing with N-channel FETs. P-channel FETs are possible
but are never used at microwave frequencies, because they would
have far worse performance compared to N-channel FETs. Go ask a
device guy why that is and he will explain to you something about
the electron mobility of the device, but who really cares? The
drain and source contacts are connected to the channel with ohmic
metal contacts that form low-resistance connections to these terminals.
The gate connection to the channel is formed between the drain and
source by a Schottky metal contact to the channel. The rectifying
property of the gate contact means that when it is reverse biased
with respect to the channel it conducts almost zero DC current (IGS)
to the channel, but its electric field can be used to effectively
displace the electrons within the channel. Thus an AC voltage incident
on the gate terminal causes a variable resistance between the source
and drain of the FET. When the gate reaches pinch-off voltage the
electrons below the gate are depleted to the point where essentially
no current can flow from drain to source.
The source connection is the
"source" of electrons in the channel, and the drain is
where they are "drained off". Remember that we are talking
about electrons flowing here, and you will see that the direction
of current flow is positive from drain to source.
FET geometry refers to the physical
dimensions of a FET. FET dimensions are always described in microns
or millimeters, never in mils, with the exception that overall chip
dimensions (length, width and thickness) as often given in mils
as well as microns. This is because the next higher assembly (artwork
for a thin-film network for example) is often dimensioned in inches.
Gate length is often confused
with gate width. Just remember when you look at a gate finger,
gate length is the short dimension and gate width
is the long dimension. This is illustrated in the figure below.
Gate length has a major effect on maximum frequency of operation:
one-micron gates start to suck wind at C-band, half-micron gates
are good through X-band, quarter-micron gates are good into Ka-band,
and 0.15 micron gates can work up through W-band. What is the limit
on gate length? We aren't there yet, some companies are experimenting
with 50 to 100 nanometer gates!
Gate width refers to the unit
width of the gate as it passes between the source and drain across
the mesa (the semiconducting area of a FET). Wider gates mean more
DC and RF current, and therefore more power capability. Gate width
must be sized appropriate to frequency: if the gate width starts
to become an appreciable fraction of a wavelength, the RF performance
of the FET starts to suffer. At X-band, power FETs often have 150
um wide gates. At Ka-band the the gate width is typically 75 micron
maximum. At W-band perhaps 40 micron fingers is the upper limit.
versus gate length
A gate finger refers to
a single gate structure. Gate periphery
is the total size of a FET. Most FETs have multiple gate fingers,
so the periphery is equal to the number of gate fingers times the
unit gate width. In the example figure there are four gate fingers.
Many of the FET parameters can be directly scaled with gate periphery,
for example the saturated drain current is proportional to gate
The gate bus-bar is the
electrical contact that is used to connect all of the multiple gate
fingers together. The drain bus bar serves a similar purpose.
holes are what connect the source (or individual sources) to
the chip backside metal, which is considered RF and DC ground.
When individual sources are grounded with separate via holes, these
vias are referred to as ISVs which stands for individual
source vias. ISVs are only used on very thin FETs, perhaps with
two mils (50 microns) maximum thickness. ISVs provide very low-inductance
grounding to the source connection, providing the most gain and
efficiency for power amplifiers, which becomes more important for
power FETs operating at millimeter-wave frequencies. On four-mil
GaAs and thicker, ISVs are not usually possible, because the source
contact pad is typically smaller than the minimum diameter of an
etched via hole.
Mushroom gate or tee
gate refers to a technique of providing very short effective
gate length, while providing low gate resistance. Gate resistance
is a parasitic element that affects the maximum available gain of
a FET, and is inversely proportional to the cross-sectional area
of metal along the gate finger. A picture of a tee-gate is shown
below. This type of structure involves extra process steps and
is therefore used only in higher-frequency applications where short
gates are required, such as X-band through millimeter-waves.
A tee gate
to FET FAQs:
Why use GaAs?
The FET is built on top of a
semi-insulating substrate, most often GaAs. When we say “semi-insulating”
this is perhaps misleading. In its pure form, GaAs is remarkable
insulator, which is what makes monolithic microwave integrated circuits
(MMICs) practical. Here is one advantage GaAs has over silicon.
Pure silicon is a better conductor than pure GaAs, so it tends to
dissipate electrical fields that are needed to support transmission
modes and hence needs some "help" to be used as a MMIC.
We'll discuss that later.
a compound semiconductor?
GaAs is referred to as a “compound
semiconductor”, because it is a crystal of more than one element.
Silicon is a semiconductor all by itself. GaAs wafers are available
in up to six inch diameter, but more often FET and MMIC manufacturers
use four-inch material.
What does III-V semiconductor
Three-five material refers to
compound semiconductors made from one element from Group III on
the periodic chart (gallium in the case of GaAs) and one from Group
V (arsenic in the case of GaAs). Thanks to Luis, we just corrected
that statement in March 2011, it was backwards for the past five
years! Other three-five (or III-V in Roman numerals) semiconductors
include indium phosphide and gallium nitride. TriQuint Semiconductor
derived their name from the III-V material that their business is
based on (GaAs, of course!)
The short answer is "yes",
although I have seen a person eat a MMIC and live just to prove
this wrong. Gallium arsenide may not kill you, but it has a nasty
habit of breaking down into gallium and arsenide if left in your
town dump or incinerator. Traces of arsenide in water cause cancer,
while small doses are quite lethal. Remember the play "Arsenic
and Old Lace"?
In the United states the GaAs
industry has strict controls on what they can flush into the wastewater
stream. Even though they saw, etch, and polish tons of GaAs wafers
each year, GaAs foundries have some clever ways of separating out
the bad stuff before it goes down the drain, so give them credit
for being good citizens.
The EPA's specification on arsenic
in drinking water is 50 parts per billion. Check out your
water bill next month, we often go over this limit. Could it be
the 130 million cell phones (65,000 tons) that get discarded every
year are putting us over the top? Damn right, and wireless trash
contributes a plethora of poisonous substances to your community,
associated with cancer and a range of reproductive, neurological
and developmental disorders, including:
We predict that someday your
wireless service provider will have to take care of safely disposing
your obsolete or broken phone equipment. Until then it's your responsibility.
One option is to check out Charitable
Recycling, a U.S. charitable organization (duh) that pays a
dollar to charity for every unwanted cell phone turned in. Then
they fix up the phones and donate them to needy people all over
the world. Hopefully these needy people don't burn your little gift
to keep their mud hut warm! You can go to their site for information
about local collection sites and the charities they support. Perhaps
a better option is the
Rechargeable Battery Recycling program available at many places
where you buy batteries (like Sears, Home Depot, Ace Hardware and
“bandgap” refer to?
Bandgap is a material property
that takes some knowledge of semiconductor physics to understand.
Who cares? You might. The higher the bandgap, the higher the breakdown
voltage the material can support. High breakdown is a huge advantage
for power amplifiers, remember Ohm’s law and you will see that voltage
swing is proportional to power. GaAs is a medium bandgap technology
at 1.5 electron-volts, you can get 20 volts breakdown on a good
day with a GaAs MESFET. InP is a low-bandgap device at 0.75 electron-volts,
it only supports a few volts breakdown. The “great white hope”
(is that politically incorrect or what?) of microwave semiconductors
is gallium nitride, which is a wide bandgap semiconductor at greater
than 3 electron-volts bandgap energy. GaN FETs have exhibited over
100 volts breakdown voltage. DARPA is a big fan of GaN technology
and is spending tens of millions of taxpayer dollars trying to develop
this technology beyond a laboratory curiosity that blows up in a
few hours of operation into the "next big thing" for solid-state
is the difference between Schottky and Ohmic contacts?
Ohmic metal on a FET is often
called "source-drain metal". This is because it
forms the contacts for these two terminals of the FET. The drain
and source contacts are considered “ohmic” because they behave resistively,
that is, they pass current in either direction, obeying Ohm’s law
where current is proportional to voltage. Ohmic metal is usually
the first layer of metal applied when a FET or a MMIC is fabricated.
It is alloyed at high temperature.
What is a Schottky contact?
It is a diode junction formed between certain metals and semiconductors.
You can read about the illustrious
Mr. Schottky here. Metals that form Schottky contacts to N-type
GaAs include aluminum, gold, silver, titanium and platinum. Often
a layered structure of metals is used in FETs, such as titanium/platinum/gold
(Ti/Pt/Au). Gold reacts with GaAs so it is a bad Schottky metal.
Platinum keeps the gold away from the GaAs (it acts as a barrier
metal in this case). Titanium is what makes the gate "stick"
to the GaAs.
What does semiconductor refer
Based on differences in bulk
resistivity, five classes of materials are in common usage, namely
conductors, semiconductors, semi-insulators, insulators and superconductors.
There is no IEEE standard for these categories, and if someone can
supply a good reference on this point we'd appreciate it! Click
here for the Microwaves101 version of the definition of these
GaAs bulk resistivity can be
tailored over a huge range, 10-6 to 1022,
so that GaAs can be anywhere from a conductor to an insulator. By
doping Chrome is usually added to the melt to raise resistivity,
but this trick has its limitations (it does not stay stable through
wafer processing steps). High purity, undoped GaAs can be 107
to 108 ohm-cm.
Intrinsic versus extrinsic GaAs? intrinsic refers to the pure crystal, extrinsic refers to the
doped material where conduction is due to donor or acceptors.
Thermal conductivity of FETs
The thermal conductivity (TC)
of GaAs varies at 1/T (T in Kelvin). It is approximately 0.55 W/cm-C
at room temperature.
FETs and MMICs are made
This discussion got so big we
had to put it on a separate page! Click
here to check out our latest description of microwave semiconductor
IV and Transfer Curves
The operation of any three-terminal
device is well described on a three dimensional surface plot as
shown below. For an FET, the output characteristics VDS and IDS
are shown to be a function of the input voltage VGS. A typical
FET response is shown below.
FET IV characteristics
The three-dimensional characteristics
are most often collapsed onto 2-D plots of IV curves, as shown below.
Here the output drain current/voltage relationship is plotted at
discrete gate voltages. Such a plot can be produced from a FET
using any Tektronics curve tracer.
Depicted on this plot are some definitions:
the drain-source current when the gate is forward biased for maximum
channel current. This is typically measured at up to 1.0 volts
on the gate (higher potentials will conduct tons of current across
the gate Schottky contact which tends to roast your FET) and perhaps
1.5 or 2 Volts drain-to-source. To get to IMAX the gate must be
raised to its Schottky barrier height (voltage), which is approximately
0.7 volts. This is the intrinsic gate bias. The other 0.3 volts
will drop across the intrinsic source resistance RS. Still, you
might want to limit the measurement current with a current-limiting
the saturated drain-source current when the gate is biased at zero
volts (grounded to the source). This is typically measured at 1.5
or 2 Volts drain-to-source.
pinch-off voltage. This is where the drain-source terminals start
to look like an open circuit, and no appreciable current flows even
at high drain-source potentials. In practice there is always some
residual current and the actual VPO measurement must make an allowance
for this. For example, the pinch-off voltage could be measured
at 2.5% of IDSS and VDS=2 volts.
the gate-drain breakdown voltage, which is indirectly measured on
the IV curves. At high drain-source potential and near pinch-off,
the IV curves tend to bend up. As shown in the picture the breakdown
voltage VDS is approximately 10 volts (VGS=-4 volts and VDS=6 volts
combined). Stay away from this bias region if you want your FET
to have a long and happy life!
the voltage at which the curves transition from "linear"
to "saturation". In the linear region, IDS depends on
both VGS and VDS (from VDS=0 Volts to approximately VDS=2 Volts).
In the saturation region, IDS depends mainly on VGS and not VDS.
This is the right side of the curve, beyond VDS=2 volts..
FET IV characteristics
Another very useful plot of the
FET’s characteristics is called the FET transfer characteristic.
Here we see the variation in drain current (thanks Karel!)
due to variation in gate voltage, at some fixed drain voltage in
the saturation region (beyond VDS=2 Volts). This is analogous to
looking at a cut in the Y-Z plane in the surface plot above. Plotted
below is the transfer characteristic of a FET. This type of plot
is extremely useful in designing self-biasing networks which are
described below. Here we see why a FET is an effective amplifier:
for a quiescent point of –1 Volts, a peak-to-peak voltage swing
of +/-0.5 Volts on the gate terminal provides a variation in drain
current from 50 to 250 mA.
Where did we get the nice transfer
curve shown in the above plot? We have developed a model that allows
the user to fit a continuous transfer curve to measured data, with
separate coefficients to fit the regions above and below VGS=0 Volts.
The equations are shown below. By using two different exponent terms,
is possible to control the ratio of IMAX/IDSS, which is impossible
in simpler models. Soon we will put a spreadsheet in the download
area that contains these equations for you to use when fitting your
own FET. Check back later! By the way, the third equation is missing
a minus sign. Find it and you've won a pen knife!
of microwave FETs
With respect to their intended
operation, FETs can be divided into three categories: low noise,
power and switch FETs. Low noise FETs are optimized to provide
the lowest possible noise figure at very low voltage and power (perhaps
1.5 volts and 10 ma). Power FETs possess higher breakdown voltage
than low noise FETs and can therefore operate at higher voltages,
and are much larger in periphery than low noise FETs.
FETs are intended to operate passively (no drain current and
no gain); the gate voltage is merely used to switch the device from
a resistive element to a small capacitive element. Switch FETs
can be configured in series with a transmission line (drain and
source act as input or output), or in shunt, with the source grounded.
One beautiful thing about switch FETs is that you don't really care
how high the gate feed resistance is, because the RF signal doesn't
traverse the gate terminal. This opens up many possibilities when
you design the gate structure. One type of switch FET is called
a "meandered gate" FET. This means that multiple
FET gates are hooked up in series, rather than through a single
“depletion mode” FET is one where the gate is mainly used to reduce
the current within the channel (most common microwave FETs are depletion
mode). An “enhancement mode” FET does not conduct drain-to-source
until the gate is slightly forward biased. Think of this as a depletion-mode
FET with a zero-volt pinch-off voltage. There is a big limitation
to enhancement-mode FETs: you can’t exceed the turn-on voltage
of the Schottky contact, which is typically 0.7 volts, so the gate
etching process has to be well-controlled to produce a FET with
pinch-off of zero volts or perhaps a few tenths of a positive volt.
Etch too far and you will end up with no FET at all, just a capacitor
between drain and source!
Bias networks are what are used
to put a FET at the intended quiescent operating
point. For example, you might want to operate a FET in a power
amplifier at 6 volts VDS and at 50% of the saturated drain current
(IDSS/2). This is the quiescent point.
You might want to check out our
page on bias tees and our page
element bias tee design.
FET DC characteristics, such
as IDSS and VPO vary from lot to lot, and even within a wafer.
This complicates the life of the amplifier designer, since VGS needs
to be set to achieve either a fixed fraction of the saturated drain
current, or a fixed current. One amplifier might need VGS to be
–1.05 volts, another might need VGS =-2.1 volts to perform as designed.
What’s a designer to do?
There are at least three ways
to bias up a FET amplifier to get to the intended quiescent operating
point. The most obvious is to have separate DC power supplies for
the gate and drain connections, with the gate supply being adjustable,
and ground the source. Grounding the source directly will provide
the most gain from the FET, which is why this is a good idea if
efficiency is a concern. In practice, the “adjustable” gate bias
supply is often a fixed supply of perhaps –5 Volts, with an adjustable
resistor-divider network being employed to supply the needed gate
Another method of biasing a FET
is with an active bias network. This
is an analog circuit that attempts to eliminate any manual adjustments
to the FET Q-point, by using a small FET to “calculate” the required
gate bias for the FET in the circuit and supply it to the larger
FET which is the active device in the amplifier. Such a circuit
is often called a “current mirror” and won’t be covered here at
this time. An active bias network, if designed properly, does not
reduce the overall efficiency of a power amplifier by much. However,
a negative supply voltage is still required, although it need only
be at a fixed voltage such as –5 Volts.
The third way to bias a FET is
to employ a “self-biasing” network, in
which a resistor of a strategic value is placed between the source
connection and ground. The resistor is bypassed with a capacitor
so that the FET source connection sees a zero-Ohm connection to
ground at the operating frequency. When drain current flows through
the FET and then through the source resistor, the source voltage
rises above ground. The gate voltage is either held at a fixed
voltage or grounded, resulting in a fixed negative gate-source voltage,
which is (hopefully) the intended Q-point. For example, if the
gate was grounded, and the FET was drawing 200 ma of drain current
through a 10-ohm source resistor, the gate-source bias would be
–2 volts. The major advantage of the self-bias scheme over other
bias schemes is that only a single positive voltage supply is needed
to power up the amplifier. The downsides to using self-bias schemes
are that amplifier efficiency is lost due to the voltage drop of
the source resistor. Also, the FET cannot be RF grounded at all
frequencies as well as if it was DC grounded with via holes, so
gain and efficiency can be degraded as a result. Self-bias networks
are often used in LNAs, but not power amplifiers, for these two
with raised gate voltage
The self-bias network is used
to eliminate the need for a negative voltage to a FET-based amplifier.
One of the ways to make a design less susceptible to normal variations
in FET transfer characteristics (the gate voltage needed to induce
a fixed drain current) is to raise the gate bias above ground.
Such designs are often called “raised gate bias” designs. Duh!
Below we will prove to you that raised gate bias designs are advantageous
in this regard. We also will supply you with an Excel spreadsheet
where you can analyze your particular design to make it immune to
variations in pinch-off voltage and IDSS.
These comments are from James,
a semiconductor guy with some RF test experience, submitted in July
2005. We'll distribute them around the page in appropriate places
when we get a chance...
The importance of gate inductance
can't be over-emphasized for mm wave operation. In most cases the
gate finger inductance will limit finger width to small fractions
of a wavelength. It is controlling the gate inductance, too, which
is the primary driver for the use of tee gates.
All FETs run up against a
simple geometrical constraint: the channel has to scale down at
least in proportion to the gate length, or gate control of the current
is lost. This makes it hard to get power densities out of short
InP actually has a bandgap
of around 1.35 eV, but most InP based FETs have InGaAs based channels,
which do have bandgaps around 0.75eV.
Most contacts (ohmic or Schottky)
to compound semiconductors are far from perfectly stable over time.
Some Schottky contacts might not be stable in the presence of hydrogen
from, say, plated packages.
The thermal conductivity of
GaAs is basically miserable, and ternary layers are far worse.