Updated July 19,
here to go to our main page on semiconductor tradeoffs
This page was contributed by
Andrei during June 2006, a true friend of Microwaves101! We have
only done some minor edits, Andrei is the subject matter expert,
not us. If anyone wants to contribute material on other semiconductor
technologues, by all means contact us.
The story behind LDMOS is quite
sad for everyone outside silicon (you GaAs
people know what we're talking about), because LDMOS is a real winner.
A corollary of Moore's law is, "everything that can
be made of silicon, should be made of silicon!"
LDMOS stands for lateral double-diffused
MOSFET, the lateral version of power MOSFET, DMOS. Although some
vendors offer RF versions of DMOS, its vertical structure has serious
problems with excessive parasitic capacitance starting at around
500 MHz. LDMOS fares much better at higher frequencies, not least
due to extensive technology development recent years. The first
cellular base stations used silicon BJTs, and many GaAs developers
expected an easy win as cell frequencies were going up, and linearity
and efficiency requirements were getting tighter. This never happened,
it was LDMOS that invaded the territory. LDMOS components with output
power over 100 Watts at 2.7 GHz are available at the moment of writing
this. The frequency range is likely to extend further as Freescale
has recently announced 3.5 GHz high power LDMOS for coming WiMAX
applications. If or when this happens, the hopes AlGaN developers
had for exciting new markets might not come true, just as those
of GaAs folks a decade ago.
High power LDMOS devices typically
provide internal impedance matching for intended frequency band.
The practical power limit for LDMOS without internal matching is
around 10 Watts at 2.5 GHz. This might leave a window of opportunity
for other materials in broadband power designs. Wide bandgap materials
offer higher output power per 1 pF of gate capacitance, which is
an advantage for broadband applications.
Comments on LDMOS device technology
What is so special with LDMOS?
As a device of MOSFET variety, LDMOS uses an inversion channel at
the silicon-oxide interface. The inversion channel is induced under
the gate by positive gate potential. Under practically relevant
conditions the inversion layer only exists over the laterally diffused
P-well, which is sometimes called depletion stopper. As the electrons
leave the region over the stopper they are picked up by the electric
field due to positive drain bias and abandon the inversion channel
going deeper into the bulk. The effective gate length defines the
lateral extension of the stopper layer. It may be therefore shorter
than the physical length of the gate electrode.
The cross-section below was borrowed
from a report by A. Litwin at a small workshop at Chalmers. Hope
he doesn't mind!
GaAs MESFETs and HEMTs with very
short gates suffer from high output conductance due to short-channel
effects. In a standard MESFET, high electric field from the drain
side penetrates underneath the channel. A parasitic channel may
be formed at a high drain bias, which penetrates through the buffer
and/or substrate, i.e. underneath the nominal physical channel layer.
The problem becomes more and more pronounced as one decreases the
gate length and increases the drain bias. In silicon LDMOS the short-channel
effect is taken care of by the P-type depletion stopper. In addition
to the depletion stopper underneath the channel, most of recent
LDMOS designs also use a field plate on the top, which overlaps
thick dielectric over gate and provides additional shielding of
the gate from the drain potential. Combined action of stopper and
field plate minimizes the feedback (drain-to-gate) capacitance,
which means further improvement of RF signal gain.
High breakdown voltage of LDMOS
is one of its most important advantages. For a given output impedance
the power output is the square of voltage swing, therefore you get
over 7 dB more power going from 12 to 28 Vdd. Even if you are able
to match that low-voltage component you will lose some bandwidth
and you will certainly need a lot of current out of your power supply.
So why does LDMOS have higher operation voltage than silicon than
GaAs MESFET if the breakdown field in GaAs is higher than in silicon?
Examination of the cross-sections will give the answer to this question.
Electric field crowding at the gate edge of the MESFET takes up
all the advantages of the higher breakdown field of GaAs. In addition,
the current pathway through the buffer layer does
not offer the designer much choice apart from increasing the gate
length to make a tradeoff between gain and output power. In LDMOS
the depletion stopper and the field plate form a fairly uniform
electric field between gate and drain. Electric field crowding at
the apparently sharp edge of the field plate has little effect on
the breakdown in LDMOS, since the breakdown field of the oxide is
30X that of silicon.
LDMOS utilizes epitaxial silicon,
low-doped P-type layers grown on low-resistivity (i.e. highly doped)
silicon wafers. Either a diffused sinker or a trench etched through
the epitaxial layer is used to ground the source to the substrate.
Each source is comfortably grounded to the baseplate, as you get
it in a high-end GaAs HEMT with individual source vias. Gate and
drain impedance is pre-matched using lumped element technique. Bondwires
are used as inductors and extra capacitor chips are soldered next
to the LDMOS chip into the same package. 50-Ohm components are available,
although those with the highest output power are push-pull and are
often matched to lower impedance, anywhere between a few Ohms and
One cannot go in too much detail
about the power capabilities of LDMOS, as we don't have any discussion/demystification
of AB class operation on the site. That's why we cannot discuss
efficiency and linearity for CDMA-type signal transmission here!.