Multi-state simulation of phase shifters

Updated December 30, 2009

Click here to go to our main page on phase shifters

Click here to learn about RMS errors

Click here to learn an important characteristic of phase shifters if you want to use them in a phased array

Click here to learn about phased arrays

On this page you will learn how to create a ADS file that drives a multi-state phase shifter design and crunches out its RMS errors. Maybe we'll even add some Monte-Carlo variations to it one of these days.

Phase shifter designers might want you to think that it takes two months to design a phase shifter. In reality, it doesn't take very long, once you have the files set up. It's just a matter of selecting the best bit topologies, setting their center frequency, hitting the optimize button for each bit individually, layout and EM analysis, then connecting the bits taught in a multi-state file and selecting bit order based on VSWR effects of the individual bits beating against each other. Phase shifter designers probably spend more time on Facebook than they do on the Smith chart!

Main schematic

Behold the ADS schematic below, it has everything you need. It's not 100% idiot proof, which is OK, because we want to screen out potential idiots from designing phase shifters...

There are three two-port networks in the schematic. Between ports 1 and 2, we have the four-bit phase shifter in its reference state, which Microwaves101 defines as the "electrically shortest" phase state. Between ports 3 and 4, we have the phase shifter that ratchets through all of its phase states, in the example we have four bits, so there are sixteen states. Between ports 5 and 6, we have the ideal phase states, in this case, 0, 22.5, 45, 90... degrees.

The schematic as shown is impossible to read. If you click on it you will find a slightly more readable one; if anyone has any suggestions for exporting ADS schematic files into a readable graphic image for a web page, we'd like to hear about it. This remains a big challenge that we waste a lot of time on!

Driving the phase bits

This is perhaps the most clever thing you will learn from this web page... how to create the binary sequence that drives the phase bits in a multi-state simulation. There are other ways to do this of course, but you won't find any described anywhere on the worldwide web.

ADS sweeps frequency in normal S-parameter simulations. In this multi-state case, we also need it to sweep sixteen phase states. This is done by variable "Xstate" that we define, which starts at 1 and stops at 16 (for this four-bit simulation), and controlled by the "parameter sweep" token. We also have to preset it equal to a number in the "VAR1" token, this is an ADS quirk which can't be explained.

Xstate is used to control four variables, B1, B2, B3 and B4. These form a binary sequence, and control the four phase bits. B1 is the least significant bit (22.5 degrees), while B4 is the most (180 degrees). These are set up by token "VAR2", and some fancy-pants math. We used the remainder and integer functions to come up with the state table, which is shown below.

Here's the equations for B1 through B4. If you need to modify this for a five, six, or seven bit phase shifter, You don't have to be a member of Mensa to follow the pattern.

B1=rem(int(Xstate,2))

B2=rem(int(Xstate/2,2))

B3=rem(int(Xstate/4,2))

B4=rem(int(xstate/8,2))

The rest of the schematic

Bit order is shown when you click into the "Four-bit_PS" element. Here four parameterized sub-circuits are cascaded, with the desired phase shift ("PS") and controlled by the "ON parameter. So, where is the 180 bit, you might ask? These particular subcircuits provide balanced phase shifts in positive and negative direction, so if you want 180 degrees total, you input 90 degrees. This is nothing special, just an accident of birth.

By clicking into any one of the phase bits (they all use the same schematic with different input parameters), the high-pass/low-pass schematic is revealed (see below). This high-pass/low-pass bit has equations that calculate the lumped element values from the specified phase shift (PS), center frequency (FC) and system impedance (Z0). The resistors R1 and R2 are used to connect the desired tee network depending on the value of "ON". The upper tee network provides positive phase shift, the bottom one provides negative phase shift. Thus the upper arm is the reference state.

Multi-state graphs

RMS error calculations

Here's the RMS amplitude and phase. Now you can admire the wide bandwidth afforded by the ideal high-pass low-pass phase shifter bits!

The equations for RMS errors are not exactly self explanatory. You can learn more about them on this page. We'll add to this deiscription later, please email us if you have any questions or comments!