Amp Designer 101!
here to go to our main page on amplifiers
here to go to our page on efficiency
to go to our page on FETs
This page provides instructions on a spreadsheet
that will help you floor-plan a power amp! By "floor plan",
we mean determining the correct transistor peripheries (sizes) and
bias points to achieve a given power level while maximizing efficiency.
Even with this tool, you may need to design a few failures before
you nail a design. Like Alanis Morrisette said, you lose, you learn!
The Excel file we will discuss
is in our download area.
Before we get started, keep in mind that floor planning a power amplifier
represents less than 10% of the work required to actually execute
a design, unless you are using pre-matched transistors. The complete
design will require the use of expensive EDA software
for designing matching networks and laying out the circuit. But
getting the floor plan right is a critical part of the exercise,
no doubt about it.
The efficiency calculations
can be reviewed on this page.
In designing a power amp, the
first thing you need to consider is how much power you need to obtain,
and whether there are any special considerations on linearity. In
a radar it doesn't matter much if your power amp is six dB into
compression, but in a communication system it matters a lot. For
now we'll assume the radar case.
Let's define a couple of terms
on this page first:
This phrase comes up when you are discussing what semiconductor
to use. Technology platform could be SiGe HBT, GaAs PHEMT or InP
PHEMT for examples. While we're on the subject of technology, let's
make one thing crystal clear. Anyone who uses the term "tech"
in place of the word "technology" is a lightweight and
should be fired during the third Bush Recession. Then they'd have
more time to sit about reading
PopSci or other dumbed-down science publications that exist
mainly to sell male enhancement products to lonely would-be geeks.
Reserve the phrase "high tech" to throwaway gadgets, not
real design work.
This is a measure of the size of a transistor. The periphery of
a FET is measured in linear dimension of
the gate width, in microns or millimeters. If you are dealing with
vertical structures such as HBTs, the periphery is measured in area
(usually micron^2). We'll use the convention that we are dealing
with FETs, you can't please everyone!
The ratio of the sizes of stage N to stage N-1, the higher the
periphery ratio, the sportier the design, meaning you walk a fine
line between setting a new industry benchmark versus your design
going down in flames because you don't have enough drive to the
This is a measure of power divided by transistors size. In the case
of FETs it is expressed in watts/mm. In olden times GaAs MESFETs
struggled to achieve power densities beyond 1 watt/mm. Soon we will
see in production GaN transistors with more than 10W/mm power density.
Saturated output power (PSAT)
This is the output power where the Pin/Pout curve slope goes to
zero. This is the most you can get!
Selecting the technology platform
You need to consider what technology
your power amp will use, and gain, efficiency, power density, etc.
it can provide. Possibilities include MESFETs, PHEMTs or HBTs. Try
to come up with something that can provide at least 10 dB small-signal
available gain (GMAX) or your efficiency
will be low. With 10 dB gain available, it is usually no problem
to arrive at matching networks with 10-20% bandwidth that will provide
at least 7 or 8 dB small signal gain and perhaps 5 to 6 dB under
saturated drive. You should also obtain some load-pull Pin/Pout
curves (including gain and efficiency) of the representative technology
so you'll know what the best efficiency you can expect is. Check
out our page on load pull so you'll know
what we are talking about.
How much compression should
each stage have?
The output stage should exhibit
the most gain compression, plan on at least 2 dB to get close to
maximum power (Psat). The second to last stage also needs to compress,
but you want to have some design margin so design it to operate
at only one dB compression when it is saturating the final stage.
Oversize the prior stages so they operate linearly or just slightly
How much loss is in the matching
The resistive loss of transmission
lines is inescapable. But it can be minimized.
More on this later...
Resistors in drain supply networks?
Lots of amplifiers use resistors
in the drain supply lines (thanks to Chris, who pointed out that drain terminal does not actually bias the amplifier), in order to reduce the voltage on the earlier
stages, or to improve RF stability. In a power amp the bias resistors
reduce efficiency, but everything is a compromise, right? In any
case we considered that you might want to use bias resisters when
we put together the spreadsheet.
How close to maximum efficiency
can I operate each stage?
Here's what we recommend: the
output stage is the only stage that you should try to operate at
the best efficiency. If the technology platform is capable of 55%
drain efficiency at 2 dB gain compression, that's a good goal for
the final stage. Then back off the third stage to 40% efficiency,
the second stage to 30%, and the first stage to 20%. This is necessary
because it is nearly impossible to design perfect matching networks
that will provide the optimum load at center frequency and provide
stable operation from DC to light.
Now on to the spreadsheet!
There are probably a thousand
version of such a spreadsheet, and every designer has his own preferences.
We made two versions to try to satisfy a wider audience. Feel free
to give us feedback if you have a better idea.
Each stage in the spreadsheet
includes a FET (or multiple FETs in parallel), and input matching
network and an output matching network, and a bias resistor. The
input and output matching networks contribute RF loss (which is
entered in dB), while the bias resistor contributes DC voltage drop,
another power loss that reduces efficiency.
Here's all of the variables
in the version that appears on Sheet1:
- Output power (watts)
- FET periphery in millimeters
(number of fingers x unit finger width)
- Bias voltage in volts
- Bias current density in mA/mm
- Bias network resistance in
- Input matching network loss
- Output matching network loss
- Transistor gain in dB
- Transistor gain compression
From these variables, the drain
efficiencies and power added efficiencies of each stage are all
calculated. It's up to you to determine what is reasonable for each
stage, just because you can floor plan an amplifier with each stage
operating at 40% efficiency doesn't mean you can build it.
The second worksheet (Sheet2)
performs the same calculations but the drain efficiency is now an
independent variable. You enter drain efficiency (rather than device
periphery), and the spreadsheet calculates the drain current and
current density. Again, it's up to you to input realistic values.
Time for an example!
Suppose you were planning on
a 20 GHz amplifier using 0.25 micron pHEMT technology. You'd go
to a foundry and get information on IV curves, operating voltage,
and maximum available gain. Here's some info we gleaned from the
web from the "T-word" company. If they decide to sponsor
a page here we'll go in the tank for them and even reveal their
Here's some IV curves. Normalizing
to 1mm periphery we see that IDSS (VGS=0 volts) is 240 ma/mm, IMAX
is about 470. We'll pick an operating point at
Here's the available gain. Although
it isn't measured at a "power bias", we'll assume that
the gain doesn't change much when you increase the voltage to 8
volts (the maximum recommended voltage is 9 volts, but why push your
luck...) At 20 GHz we see 12 dB gain, plenty of gain for an efficient
Next here's a loadpull result
at 9 volts, tuned for best efficiency. A true Bazooka Joe graph,
this is gonna take some time to pull off the numbers that we need.
Let's assume this is a hero result and back off a little. We'll
plan for 50% power-added efficiency for the final stage in our design.
The compression of the device is very soft, it is compressed at
28 dBm output power.
This is probably an 8x100 micron
device but that level of detail isn't provided. The output power
at maximum efficiency is ~28 dBm, or 630 mW. Normalizing to 1mm
periphery reveals that the power capability is about 790 mw/mm.
What really sucks is that they
didn't provide DC current on the plot. We'll have to reverse engineer
Note: these images are mere placeholders,
they have little to do with the design we are looking at.
What if I only want to design
a two-stage or three-stage amp?
For now, just enter 0 dB gain,
compression and matching network losses on the stages you don't
need, starting from the left. We'll try to automate this in the
Comments or questions? Please