RF printed wiring board hints

Updated June 25, 2010

New for March 2008! This material came from Greg. It's some random notes on RF PWBs that are meant to convey some insights into designing for RF performance as well as low cost.

Introduction

RF printed wiring boards exist as interfaces for and interconnects between RF components and external parts (e.g., antennas, digital processors) and as a structure upon which the RF components can be mounted before insertion into a housing. Components can include passives like couplers or power dividers, filters, or active components such as amplifiers.

An RF PWB and other substrates (such as ceramics) differ in cost and performance. They typically serve the same, basic functions. Size, frequency, and application are unimportant when it comes to general design practices. If an engineer can design RF PWBs then he can design System in Package (SiP) substrates and circuit card assemblies (CCAs). More exotic options such as low temperature co-fired ceramic provide the engineer additional capability, such as integrating filters and even the potential to incorporate ferrite-based passives into the substrates in exchange for higher price and longer development and production times.

Applications include commercial and defense, low cost and high performance. Design approaches include high detail, extensive modeling using hundreds of thousands of dollars worth of specialized software and quick turn prototypes with simple CAD layouts. Sketches on paper napkins still exist, but need to be redrawn on a computer at some point before they're manufactured. The best designs (lowest cost, shortest schedule, highest performance) usually include BOTH highly detailed models to simulate and analyze performance with quick turn prototypes to verify isolation, leakage, and line isolation.

If you just look at just three references…

Good general resource for PWBs that covers electrical and mechanical considerations:
http://www.ieee.li/pdf/viewgraphs_pwb_design.pdf

Good reference for transmission lines
Transmission Line Design Handbook, by Brian Wadell

Good free calculator
AppCad, http://www.hp.woodshot.com/ originally developed by HP (and there are many more calculators out there)

Helpful Rules of Thumb

Manufacturing rules of thumb

As clock rates increase, everything below will become more and more applicable to digital designs. Digital designers have their own rules of thumb and the best RF board probably comply with digital rules, too. Howard Johnson's High Speed Digital Design: A Handbook of Black Magic is a good reference (and a good title).

Single layer RF boards are almost non-existent RF traces need good ground references and only coplanar stripline meets this requirement. Relying on a metal surface beneath the board as a good ground reference is risky because it assumes good continuity between the bottom of the board and the metal surface with no gaps. This becomes even more risky in a dynamic environment (e.g. automotive or aeronautic) when vibration may create a time variant gap.

Double layer RF board see very restricted use. The bottom layer provides a good ground reference for the RF traces, but space for DC power (voltage) distribution is very limited to spaces not used for RF traces. Only the simplest BGAs and flip chips can be used because all signals need to be routed on the top layer.

Multi-layer boards are the most common, with dedicated layers for RF traces (usually microstrip or embedded stripline), for RF signal grounds, for power planes, and, as is usually the case these days, for digital signal trace routing with additional ground planes isolating RF from digital traces.

There will never be enough layers. Layers will never have the right thickness. Line widths will never be thin enough. Loss tangents will always be too high. Dielectric constants will never be the right value. An engineer creatively navigates a path to success among all these restrictions.

Work closely with your board (or substrate) manufacturer. Their level of expertise should be tied to their cost. An engineer may have to sacrifice tight manufacturing tolerances (e.g., well controlled, well documented, or even compensated dielectric tangents) when dealing with low cost, low volume quick turn parts.

Layers cost money. Area costs money. Compact any design but do not compromise isolation between traces.

Avoid excessive parallelism - long lengths of two traces running parallel creates capacitive coupling between them. Be sure to look vertically as well as horizontally for parallel traces.

Get a copy of the manufacturer's design rules (run away if they do not have design rules - the manufacturer probably does not make RF boards). Suppliers will specify a conservative minimum trace width. Line impedance is a function of trace width and space to ground. More space to ground means more thickness. Most box designers are constrained in thickness. Smaller line widths, especially for 100 ohm differential lines, allow an engineer to achieve the desired impedance with a thickness constraint. Most suppliers require layers to be stacked symmetrically away from the center.

Bad:

Thin
Thin
Thick
Thick

Good:

Thick
Thin
Thin
Thick

Some manufacturers will have rules about % of metal coverage (more metal means less space for adhesion between layers), but this usually applies more to ceramic substrates than organic substrates such as FR-4, polyimide, or Rogers materials.

Remember that trace width will vary and smaller width traces (such as 100 ohm differential line with thin layers) will be more susceptible to impedance variations.

Prototyping boards or section of boards enables the engineer to quantify signal leakage and find sneak paths that even the best simulation may not calculate.

Electrical rules of thumb

For any analog design, ground planes should not be used for power. Ground is ground and power has a voltage on it.

Vias are a necessary evil. They add inductance (and to first order can be modeled as a short wire inductor) but allow RF traces and power to be moved to interior layers and isolated from outside EMI and RF interference. There are three types of vias - through hole, blind, and blind and buried. Through hole vias run through the whole height of the board. Blind vias start on one side of the board (usually the top) but terminate inside the board. Blind and buried vias can begin and end at any layer of the board. Vias that terminate on both ends are the cheapest. Any extra via length can act as a tuning stub, or worse, an antenna. Vias that both begin and end at internal board layers are the most expensive. Internal vias can also collapse with no visible indication. As always, performance must be traded with robustness and cost.

Ground pour on the board surface is a good way to minimize the impact of outside EMI and RF interference.

Ground pour should be kept at least 3x line width away from any RF trace. If ground pour is more than 5x line width, then the engineer can probably compact the design and save space (and cost).

The more spread out a design, the less likely it is to experience crosstalk. The more spread out a design, the more expensive it will be. The more compact a design, the more analysis (or prototype versions) will be required to assess and eliminate signal crosstalk. Match the design to the application - a simple test board should be spread out to keep design costs down, while a cell phone or weapon system should be carefully simulated then compacted to meet both size and interference constraints.

Microstrip traces are common. It is simple to route, uses no inductive vias, requires only one dielectric layer, and is always isolated from digital noise internal to the PWB. It also takes up surface area that could be dedicated to components, and it can be susceptible to external EMI or RF interference.

Embedded stripline is good to route signals away from a BGA or flip chip component that already requires vias. It is isolated from both internal PWB digital noise and external EMI. It requires two dielectric layers and so costs twice as much to fabricate as microstrip.

Ground fences around the perimeter of a board create a Faraday cage. This can isolate signals inside the board from external interference and also enable stray signals to reflect back onto adjacent signals, create crosstalk, and degrade performance. Ground fences are ideally created from two rows of vias, with one row of vias offset from the other. Rows are connected with traces on every layer. In practice, there is usually not enough space to do this everywhere. The more places grounds can be tied together, the lower the inductance between them (and the less risk of ground bounce).

Conformal coating (thin layer on organic boards used to prevent corrosion) has little effect on microstrip impedance.

Large surface mount components or plastic or metal packages can change microstrip impedance of traces routed underneath. As a specific example, see "Electromagnetic simulation of a test board to support system in package testing," Surbeck and Jackson, 2003 International Microwave and Optoelectronics Conference (and write papers about your own experiences of what works so we can all learn from your experiences + papers look good on a resume!).

The simplest design tools are basic CAD drawing packages. These require the engineer to be cognizant of the manufacturer's design rules as well as good design practices (like these rules of thumb). Anywhere a question of crosstalk is raised, the engineer either has to grow the design (and pay more per board) or calculate the crosstalk (and take more time to design the board).

Specialized software packages can handle many of these tasks automatically. Agilent ADS and Ansoft Designer are simulators with layout tools available. Cadence and Mentor offer layout packages with integrated simulators. There are many other tools available from many other companies of varying cost and functionality.

Detailed analysis can be done using the Partial Element Equivalent Circuit (PEEC) method (breaking down all traces into RLC equivalent circuits with LC circuits to represent crosstalk), the Method of Moments (MoM), or Finite Element Method (FEM) analysis. PEEC can be calculated in Matlab. There are commercially available tools to do all types of analysis ranging in cost from < $10k to > $100k.

Mechanical rules of thumb

Work with the manufacturer to avoid most mechanical problems created during fabrication. Good manufacturers will know how to identify and avoid mechanical problems better than the average electrical engineer.

Be cognizant of the heat output of all components to be mounted on the board. A PWB is an insulator so the thermal path of all parts, particularly small packaged or high power parts needs to be considered. Power amplifiers are usually mounted off board for this reason. Thermal vias can be used to move heat off a part with a high power density, but additional heatsinks or thermally conductive materials may be required to prevent parts from burning out.