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One application for digital phase shifters and attenuators is in phased array systems, inside of T/R modules. The attenuator and phase shifter each contribute amplitude and phase errors. This page will tie the four calculations together, they are too big to appear all on one page!
Digital phase shifter RMS phase calculation
Separate page.
Digital phase shifter RMS amplitude calculation
Separate page.
Digital attenuator RMS amplitude calculation
New for August 2012: considering the RMS errors of attenuators was suggested by a Nameless Contributor, many thanks!
In phase shifters, we "RMS" errors over all possible states (including the reference state), by "manufacturing" a revised reference state. For attenuators, we only examine the attenuated states after we subtract out the physical reference state. Thus, there are only 2^N-1 states (31 states for a six-bit attenuator).
Not long ago, MMIC chip manufacturers would only post primary state S-parameters on their web sites, and you were out of luck if you wanted to examine and RMS all of the states. It is now more common to find posted S-parameter files for every state. But be careful what you wish for, there is nothing more mind numbing that setting up an analysis when you have 32 separate files to keep track of. The answer to this is the multi-dimensional file, or MDF. We'll cover that topic another day.
All of this attenuator RMS analysis can be done in Excel with some effort, or in EDA software such as ADS or MWO which would be much easier than in Excel.
Here is the procedure:
1. Subtract the attenuation for all states from the zero reference state. This is done in decibels, not linear. It is possible to do it in linear, but it would “favor” the lower-loss states. This will remove the insertion loss slope for all the states, and also the zero state's insertion loss from all states. The zero state means all bits are set for their reference path.
2. Subtract the ideal targeted loss from the above newly generated loss for each state. You will have to create a "circuit" that generates these values.
3. Square up and add together the errors from 2). Then divide them by total number of states, then take the square root. The total number of states are 2^N-1 where N is the number of bits; don't make the mistake of dividing by 32 when you should divide by 31 for five bits....
In systems that have a lot of bandwidth and attenuation states, often you will get high RMS errors if you calculate this way. You can reduce errors at the system level with a look-up table, which might choose the 25 dB state when you want 23 dB because it came out closer. This type of analysis is way more complicated! The picture at the right was found on the web, in a the following paper: Novel Variable Attenuator pHEMT MMIC's for Millimetre Wave Radio Applications by Nyberg et al, of Nokia. This is a very broadband three-bit effort where low loss what a key characteristic, so flat attenuation states were not a design driver. The circuit was designed for MSB of 20 dB, or 35 dB attenuation range, from 15 to 45 GHz. If you were to examine its RMS amplitude error over that range, it is likely off by several dB at the band edges. Note that if the designer had a PIN diode process, much flatter response could be achieved, but PIN diodes bring their own headaches to the table (biasing, DC dissipation, lack of availability...)
Another thing: sometimes you get a spec that calls for high MSB, like 32 dB. Then the highest attenuation state might be 63 dB. It is very hard to prevent sneak paths from ruining that intention. Just because you think you will get 63 dB attenuation doesn't mean this will happen, this requires very careful attention to detail in terms of shielding. Two microstrip lines can seem to be very far apart yet couple more than 63 dB.
Digital attenuator RMS phase calculation
Here again, we recommend RMSing the attenuator's phase errors after you subtract out the reference state. Why? Picture a phased array that has a tapered amplitude.... most of the elements are at very low (or zero) attenuation, just the outside elements are in high loss states. Because of this favoritism, we let the reference state rule the RMS phase calculation.
On the left is phase data from Hittite's HMC941, which is a five bit effort (8 dB MSB) that spans a lot of bandwidth. Phase runout in bit states usually follows a positive slope and gets worse with attenuation as it does here. If you were to use this in a phased array you would have to correct the phase using your phase shifter in conjunction with a lookup table.
Here's the RMS phase procedure for switchable attenuators:
1. Unwind the transmission phase so that it monotonically decreases (eliminate the -180/180 degree flip). This requires an "IF" and an "AND" statement in Excel: pretend BX33 is the phase of the previous point, and BX34 is the phase of the current point, here is the equation for phase unwrapping:
=IF(AND(BX34>BX33,BX34-BX33>180),BX34-BX33-360,BX34-BX33)
We took that procedure from our S-parameter Utility spreadsheet which you can download for free.
2. Subtract the phase angle for all states from the zero reference state. The zero state means all bits are set for their reference path.
3. Square up and add together the errors from 2). Then divide them by total number of states, then take the square root. The total number of states are 2^N-1 where N is the number of bits; don't make the mistake of dividing by 32 when you should divide by 31 for five bits....