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Click here to read a poem about processing GaAs
Attention, readers... please send us some material for this page, especially if you are a process person! Some graphics for our "typical process flow" might be worth a few bucks...
This discussion is applicable to discrete FETs and diodes as well as monolithic integrated circuits (MMICs or RFICs). We have divided it into three parts: producing semi-insulating wafers, growing semiconductor starting material, and wafer processing.
Microwave semiconductor people are the sorcerers of the industry. Who else could keep raising the performance of III-V semiconductors every year forever, guaranteeing you job security through countless redesigns needed to take advantage of the latest device performance?
A clickable index to this page:
Producing boules (separate page)
Growing starting material (separate page)
Semiconductor processing (this page)
Deposition, patterning and etching
Types of lithography
Typical GaAs FET process steps
Isolation
Ohmic metal (source-drain contact)
Gate recess
Gate formation (Schottky contact)
Post-gate tests
First metal
Resistor
Passivation (and capacitor dielectric)
Second metal (and airbridge)
Final-frontside tests
Backside process (thinning, vias and plating)
RF probe tests
Wafer dicing
Visual inspection
Packaging
Before we describe a "typical" wafer process flow, let's define a few processing terms.
Deposition, patterning and etching
Much of semiconductor processing come down to three activities. In the deposition step, you are depositing material uniformly across the wafer, at a controlled thickness. The material could be metal or a dielectric film. In the patterning step, you coat the wafer with photo-resist, and pattern it using light (or x-ray or electron beam) and develop it to leave a negative or positive image of the desired pattern. In the etching step, you use chemicals (such as acids) to remove the material that you don't want.
Coming soon: plated metal versus evaporated metal
Coming soon: dry etch versus wet etch versus liftoff processes
Types of lithography
PLease see our separate page on photolithography, new for January 2012!
Lithography is the process of transferring a pattern onto the wafer by selectively exposing and developing photoresist. In contact lithography, a glass plate is used that contains the pattern for the entire wafer. It is literally led against the wafer during exposure of the photoresist. In this case the entire wafer is patterned in one shot, which is the quickest way to do the job. The down side is that the mask set must be extremely accurate to hold tight tolerances across the entire dimension of the glass, which can be eight inches or more for silicon wafers. As GaAs wafer sizes increases to six inches and larger, contact masks get more and more expensive. Also, because the mask and the wafer touch each other, eventually the glass mask will wear out.
In projection lithography, the mask is comprised of a single reticle of the wafer, fabricated at a scale of perhaps 4X or 5X. A reticle is a rectangular pattern that is repeated across a wafer, but it can contain hundreds of circuits, which can be all the same, or a wide variety in a so-called "pizza mask". A wafer stepper is used to expose the wafer one reticle at a time, so it takes longer than contact lithography. However, the mask never touches the wafer, so it never wears out. Also, because the mask is smaller, it costs much less than a contact mask. Typical reticle sizes are from 10 to 20 mm square (but not necessarily square), so you might get 40 or 50 reticles on a 100 mm diameter wafer. Note that because the pattern is repeated, you can't write unique chip numbers using projection lithography, you'd have to use a contact mask or write the numbers one by one using your e-beam.
Electron-beam lithography is a form of direct-write lithography. Using E-beam lithography you can write directly to the wafer without a mask. Because an electron beam is used, rather than light, much smaller features can be resolved. Recall that wavelength is inversely related to particle momentum, and then remember that electrons are many orders of magnitude heavier than photons. This is why e-beam is almost exclusively used for writing the gates of microwave FETs, where critical dimensions can be measured in hundreds of nanometers. Another advantage of e-beam lithography is that the pattern can be changed easily, without the need to order any expensive masks. E-beam lithography is very expensive, due to the capital equipment involved as well as the time it takes to write the wafer, one gate at a time.
Photo-resist can be either positive or negative. Negative means that exposure to light will cause it to not develop. Positive photo-resist develops when exposed to light. Negative resists are far more popular than positive resists.
Typical GaAs FET process steps
Process flow from foundry to foundry can be very different in terms of the order the steps are done, the materials used and the ways the materials are deposited. We will discuss a "generic" set of process steps here, contact your favorite foundry for information on their latest recipe!
Mesa etch or isolation implant
At the start of wafer process, the entire surface of the wafer has all of the semiconductor layers grown on it. You need to isolate the thousands of individual transistors you want to manufacture. The semiconductor material is patterned and the semiconductor layers are removed in all areas except FETs and certain resistors. A wet chemical etch is often used, such as phosphoric acid. The undisturbed areas are perhaps 3 microns taller than the rest of the GaAs substrate, hence the technical term for them is "mesa".
Sometimes resistors are made using semiconductor mesas, these are usually high-value bias resistors (a few thousand ohms at one hundred ohms per square). Mesa resisters have a nonlinear I-V response similar to a FET.
Another way to deactivate the regions of the wafer that don't need semiconductor material is by isolation implant. In this case the wafer is patterned to protect the FETs and mesa resistors, and a material such as oxygen is implanted to destroy the semiconductor capability of the GaAs by disturbing the crystal lattice, making it semi-insulating. Often a combination of wet etch and isolation implant is used in GaAs processes.
Ohmic metal (source-drain contacts)
Source-drain metal is what forms the current-carrying (ohmic) contacts to the semiconductor. As such, low resistance connections are highly desirable. The word "Ohmic" means that the contact obeys Ohm's Law (V=I*R), as opposed to a Schottky contact, which has a nonlinear IV characteristic.
Source-drain metal is usually formed by evaporation, then the contacts are alloyed for the lowest possible contact resistance to the N+ GaAs. Source-drain metal is a mixture of gold/germanium and nickel or silver. Nickel is often the actual substrate contact, it has the best "sticking" properties. SD metal often uses a liftoff process. The source drain metal has to alloyed at elevated temperatures to achieve low contact resistance.
Gate recess
Gate recess and gate formation are the most critical steps in processing FETs or MMICs. The gate recess step is where the DC parameters Idss and Vpo are controlled. Gate recess can be done in one or two steps. Basically it involves wet-etching away the ohmic contact layer (N+ layer) down to the Schottky layer (right above the channel layer). Etch too far and Idss will be too low, don't etch enough and the pinch-off voltage will be too high. This is a very critical step, but modern processes incorporate "etch-stop" layers in the semiconductor structure to make the etching more forgiving (and make the pinch-off voltage more uniform across the wafer).
What's the difference between a single-recessed and a double-recessed gate? Coming soon!
Gate formation (Schottky contact)
Because of the high frequencies involved for microwave FETs, the gate length required often stretches the limits of processing with photolithography. Visible light has a wavelength on the order of one micron; defining features smaller than one micron takes a shorter-wavelength technology. This technology for GaAs FETs and MMICs is electron-beam (E-beam) lithography.
Philips and Leica are two brands of E-beam machines. Like buying a Swiss watch, you have to go to the "old country" when you want perfection... This is one of the most expensive machines you will buy if you are setting up a MMIC foundry. Today's E-beam technology can write gates down to less than 100 nanometers.
Schottky gates are typically Ti/Pt/Au. T-gate and gamma-gate structures require two levels of photo-resist.
Coming soon: self-aligned gates
Post-gate tests
Post gate tests will tell you if you have achieved the target pinch-off voltage and breakdown voltages. You must keep in mind, however, that the breakdown voltage will vary some through the remainder of the process steps.
First metal
Resistors
Resistors can be processed before the FETs are created or after. We are familiar with the "after" process.
The resistor metal is typically tantalum nitride, but some manufacturers use nichrome. A sheet resistance target of 50 ohms per square is also typical. Some manufacturers offer more than one resistor sheet resistance, this is quite handy if you have resistors in your design that have a wide range of values.
The tolerance on resistors is typically 10%, but 5% can be provided at some foundries. This is quite remarkable in that no one laser trims resistors on a MMIC.
Passivation (capacitor dielectric)
Passivation keeps unwanted elements away from the channel (atmospheric degradation), such as hydrogen (it poisons PHEMT) and oxygen (wrecks just about anything except mammals). Most MMIC foundries use the FET passivation step to provide the dielectric for metal-insulator-metal capacitors. Silicon nitride (Si3N4 ) is the industry standard, but in the future this will change as "near-hermetic" coatings are developed. The thickness of the nitride layer spells out the sheet capacitance for thin-film capacitors. The dielectric constant (Er) of Si3N4 is 7.0, therefore 2000A gives nominally 0.0003 pF/um2 sheet capacitance. Click here to learn more about microwave capacitors.
Silicon nitride Si3N4 uses PECVD plasma enhanced chemical vapor deposition. Temperature 100C to 250C gasses are dispensed over a hot wafer in a reactor. Gasses used are silane (SiH4) and ammonia (NH3), both are toxic.
Deposition rate is typically 10 nanometers/minute (100 A/minute). For 2000A Si3N4 target thickness, 20 minutes might be required.
Second metal
The second metal layer is usually the thickest metal, often 4 microns thick but up to 6 microns is offered. This is the metal that defines most transmission lines, and carries the DC current to active devices.
Final frontside test (DC)
After the second metal is developed, your wafer has hit "final-frontside". Here probes are used to check DC parameters such as pinch-off voltage, breakdown and Idss to see if the wafer is within a window of what is considered usable.
Backside processing
The term "backside processing" lumps three or four critical process steps together. After final-frontside, the wafer is flipped and mounted face-down in a high-tech wax material for backside processing. The wafer is first thinned to the thickness that the RF designers have used in their designs. This is most often 100 um (4 mils) but sometimes 75 um (3 mils) or even 50 um (2 mils). Once a wafer is thinned it is extremely fragile. Later the backside metal adds some strength to the wafer, at least enough so that it can be re-flipped for RF probing.
Next comes via etch. Vias are either wet or dry etched, all the way through the material until the bottoms of the source pads are exposed. This is a critical step that often kills the wafer yield toward the end of processing, after 90% of the money is spent.
Then comes backside plating, which results in about 3 um of pure gold covering the wafer and coating the insides of the vias, making the ground connections.
Then saw street patterns are developed and etched on the wafer and the gold is etched away. This sets up the wafer for dicing. If the wafer will have no RF probing, it is possible to dice the wafer from the backside.
If RF probing is desired, the final backside step is to flip the wafer.
RF probe
RF probing is done when the wafers are completed but are not diced. Probe data is what allows us to achieve known-good die (KGD), or as near as possible to it.
Vendors that provide RF probe equipment include Didn't Pay Us and No-link Microtech. Most probes are ground-signal-ground, but it is possible to use probes with a single ground as well.
Typically only a pair of RF probes are placed on the wafer at a time. If a circuit contains more than two RF ports, such as a SPDT switch, either two passes are made with a pair of probes, or a custom probe card with three probes and an integrated switch is used.
Dice wafer
Chips can be "singulated" by sawing, scribe and break or even chemical etching. Probably scribe and break is the most used technique, because it is the most economical.
The tolerance of chips is often better than +/- 25 micron (+/- one mil) in both length and width.
Although chemical etching is rarely used for MMIC processing, it is used in the fabrication of beam-lead devices such as certain diodes. In this case all of the material under the beam-leads is etched away.
Visual inspection
At this point an inspector must look at the finished product and decide whether it is good enough to ship. There are usually two types of inspection criteria, commercial and military. Military inspection requires examination under higher magnification than commercial inspection.
Packaging
Chips are picked from the wafer and placed in waffle packs or gel-packs for shipment. Waffle-paks come in a variety of sizes to accommodate different chips.
Gel packs are like the "sticky-note" concept. They have just enough adhesive qualities to hold down chips, but the chips can be removed carefully using tweezers. MMIC users should beware that over time and temperature, the sticky material can fatally contaminate the gold on the backside of the MMICs, so waffle packs are the preferred container. Gel packs have been known to generate ESD! And some new power amplifier technologies are on two-mil GaAs which is too fragile to be removed from a Gel pack.
Voila! Your chips are ready to ship!