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3-Bit Attenuator Example

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New for October 2020: here's a writeup of for a patent on a three-bit attenuator that ended up on the cutting floor back in the 1980s. If you can name the four inventors, you must be one of them!  You could argue that 30 years ago this might have been proprietary information, to be protected from ruthless competitors. Today. the technique described has been used by other MMIC designers. Note that the switch FET figure of merit for this process was only 211 GHz, which limited the design to X-band and below. Modern pHEMT processes are much better, so the technique can be expanded to Ka-band. Also, the MMIC process that was used provided 6 ohms/square resistors, so the shunt resistors had to be extremely long and inductive.

Here's a similar design, patented by LMCO in 1991.

ABSTRACT

A novel, three-bit (0-7dB), single chip digital attenuator is described. Chip size is 78 mils x 80 mils. Zero state insertion loss is less than 3 dB, while peak attenuation error is less that 0.5 dB at 10 GHz. Preliminary data show the attenuator operates from at least DC to 12 GHz.

Phased array radars employing MMIC-based, elemental amplifier often require dynamic gain control within either the transmit or receive path, or both. Dual-gate, variable gain amplifiers, variable attenuators, and cascaded, single bit attenuator chips have all been used in the past for this purpose, each with specific drawbacks. Dual gate devices can compromise efficiency, noise figure, temperature response and stability, and electrical response can vary drastically from wafer to wafer. Variable attenuators require complex driver circuitry. Cascaded switchable attenuator circuits, in addition to provide a consistent and predictable frequency response, require the very simplest of driver circuitry. However, they tend to exhibit unacceptably high reference state loss, requiring added gain stages.

The circuit presented here is a novel digital attenuator approach, providing the convenience of a 1db step, three-bit digital attenuator without the high loss associated with a cascaded three bit design. This was accomplished by using a single T-type attenuator topology, and using FETs to electrically switch different resistors in and out of both the series and shunt arms.

CIRCUIT THEORY

The three-bit attenuator is based on the well-known T-network shown in Figure 1. Table 1 lists the resistance and conductance values necessary to achieve 1 db steps. Table 1 also shows how the ideal values may be approximated with a binary sequence.

Figure 1: Ideal T-Attenuator

Table 1: Comparison Between Ideal Elements and Digital Elements

Simplified schematics of the three bit attenuator’s series and shunt arms are shown in Figures 2 and 3, respectively. (The elements shown in Figures 2 and 3 are ideal).

Figure 2: Ideal Series Arm

Figure 3: Ideal Shunt Arm

The attenuator uses FETs in a switching configuration. RF is isolated from the gate bias lines with 2K resistors. The equivalent circuit of the switch FET in both on and off states is shown in Figure 4 (1-mm periphery).

Figure 4: (a) FET in switching configuration (b) Complete equivalent circuit
(c) Simplified equivalent circuit

The complete three-bit circuit schematic is shown in Figure 5. Series arm FET peripheries were chosen as a compromise between current limiting under RF drive and parasitic capacitance in the off state. Two FETs in series were used in each shunt arm to increase power handling capacity and lower the parasitic capacitance of each arm. Circuit element values were optimized using SuperCompact to lower the attenuation error and to compensate for the non-ideal switching performance of the FETs.

Figure 5: Schematic of 3-bit digital attenuator

Predicted circuit performance is plotted in Figure 6. The 0db state insertion loss prediction is 2.5 db at 10 GHz, while the maximum attenuation error is less than 0.5 db. Return loss is predicted to be better than 15 db up to 12 GHz. Although not plotted, the circuit’s response extends down to DC. The upper  edge of the usable band is slightly above 12 GHz. Bandwidth is ultimately limited by the parasitic capacitances of the switch FETs.  

Figure 6: Predicted circuit performance

FABRICATION

The attenuator was fabricated using The Lazy R's Integrated Process. Si was implanted into 3” semi-insulating GaAs wafers to achieve a peak 2E18 contact and 2E17 active region. Oxygen was used for isolation. Ohmic contacts were NiGeAu with a 3.5um source-drain spacing. 0.5 um gates (TiPtAu) were defined using E-beam lithography and were recessed to achieve a 3 to 4 volt pinchoff. A separate level of TiPtAu was deposited to define capacitor bottom plates and underpasses of airbridges. Silicon nitride (0.2um) was used for passivation. Tantalum nitride (6 ohms/square) was deposited over the entire wafer and etched to define thin film resistors. Holes were then etched through the nitride to make contact to ohmic and capacitor bottom metal. Airbridge pillows were subsequently defined and 3um of Au was evaporated and lifted off to define the top level metallization. Backside processing consisted of lapping the wafers to 4 mils thickness, reactive ion etching of via holes, plating to a thickness of 5um Au, and finally saw dicing.

A layout of the circuit is shown in Figure 7. The chip is 78 mils x 80 mils. (Chip photos will be available for publication).

Figure 7: Circuit Layout

RESULTS

Figure 8 shows the measured insertion loss of the 3-bit attenuator over all states from 0.05 – 20.05 GHz. The reference state insertion loss is about 2.8 dB at 10 GHz. The peak error is about 0.5dB at 10 GHz. The degradation in the measured data above 12 GHz is partially attributed to the test fixture.

Figure 8: Measured Insertion Loss

CONCLUSIONS

A novel 3-bit T-attenuator topology is presented. This topology occupies less real estate than conventional cascaded bit designs. State of the art performance was demonstrated from DC – 12 GHz. Reference state insertion loss was 2.8 dB maximum. Peak error was 0.5 dB.

 

Author : Katerina Peterson, John Wendler, Steve Huettner

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