FET Bias Networks

New for May 2020: this page was split from our Microwave FET Tutorial.

Bias networks are what are used to put a FET at the intended quiescent operating point.  For example, you might want to operate a FET in a power amplifier at 6 volts VDS and at 50% of the saturated drain current (IDSS/2).  This is the quiescent point.

You might want to check out our page on bias tees and our page showing lumped element bias tee design.

FET DC characteristics, such as IDSS and VPO vary from lot to lot, and even within a wafer.  This complicates the life of the amplifier designer, since VGS needs to be set to achieve either a fixed fraction of the saturated drain current, or a fixed current.  One amplifier might need VGS to be "1.05 volts, another might need VGS =-2.1 volts to perform as designed.  What's a designer to do?

There are at least three ways to bias up a FET amplifier to get to the intended quiescent operating point.  The most obvious is to have separate DC power supplies for the gate and drain connections, with the gate supply being adjustable, and ground the source.  Grounding the source directly will provide the most gain from the FET, which is why this is a good idea if efficiency is a concern.  In practice, the "adjustable" gate bias supply is often a fixed supply of perhaps "5 Volts, with an adjustable resistor-divider network being employed to supply the needed gate voltage.

Another method of biasing a FET is with an active bias network.  This is an analog circuit that attempts to eliminate any manual adjustments to the FET Q-point, by using a small FET to "calculate" the required gate bias for the FET in the circuit and supply it to the larger FET which is the active device in the amplifier.  Such a circuit is often called a "current mirror" and won't be covered here at this time. An active bias network, if designed properly, does not reduce the overall efficiency of a power amplifier by much.  However, a negative supply voltage is still required, although it need only be at a fixed voltage such as "5 Volts.

The third way to bias a FET is to employ a  "self-biasing" network, in which a resistor of a strategic value is placed between the source connection and ground.  The resistor is bypassed with a capacitor so that the FET source connection sees a zero-Ohm connection to ground at the operating frequency.  When drain current flows through the FET and then through the source resistor, the source voltage rises above ground.  The gate voltage is either held at a fixed voltage or grounded, resulting in a fixed negative gate-source voltage, which is (hopefully) the intended Q-point.  For example, if the gate was grounded, and the FET was drawing 200 ma of drain current through a 10-ohm source resistor, the gate-source bias would be 2 volts.  The major advantage of the self-bias scheme over other bias schemes is that only a single positive voltage supply is needed to power up the amplifier.  The downsides to using self-bias schemes are that amplifier efficiency is lost due to the voltage drop of the source resistor.  Also, the FET cannot be RF grounded at all frequencies as well as if it was DC grounded with via holes, so gain and efficiency can be degraded as a result.  Self-bias networks are often used in LNAs, but not power amplifiers, for these two reasons.

Note that grounding the gate, as opposed to raising it to a positive value (like the image above), makes the circuit more sensitive to shifts in pinch-off voltage, but it will be more efficient.

We have a spreadsheet that will help you with designing self-biasing networks.  We'll add it to our download area soon.

Author : Unknown Editor