# Microwaves101 switch FET model

Click here to go to a new page on geometric modeling of switch FETs (under construction)

New for February 2016!

Most people are aware that a switch FET acts as either a resistor or capacitor (at least between the drain and source terminals), but are two elements really enough to model it?  No.  On this page we will show you the parasitics that matter in a switch design, in a model that we developed in AWR's Microwave Office.

Perhaps the most important innovation we have added to lumped element switch FET model is the ability to scale Figure of Merit.  If you don't have an understanding of the switch FET figure of merit, go to this page and read about it. This FOM is a good measure of how high in frequency a switch technology can go. You can use it to predict improved performance in your next IRAD proposal, and tell Mayor McCheese all the wonderful things you could do if he would cough up some money to improve your foundries switch FET technology.  Like Northrop Grumman did.

Before we continue, let's point out what this model does NOT include.  It does not include the distributed effects of drain and source fingers.  These are very important, but we will leave that conversation for another day, Grasshopper. Often, switch FET models include inductance at the source and drain terminals to account for these effects.

You may be wondering, "I'm using the blah-blah foundry's design kit, which includes a nonlinear FET model that I assume works perfectly, for any switch or amplifier FET structure, why do I need to look at a lumped element model?" Listen to yourself, you just used a non-engineering key word, "assume"....

Our lumped-element model accounts for all the parasitics that affect switch performance in the off-state, even if it is linear. If you want to know the power handling of a switch structure, you should read about it here.

Some points of interest in the model we present on this page are:

• The model is scalable by "Q" which is the periphery of the FET, in microns.
• The state is controlled by setting state=0 (the FET is off) or state=1 (FET is on).
• Figure of Merit is scalable.  We made the capacitance fixed and scaled the on-resistance.  This allows you to answer the important question: what if your process people actually did something to improve their switch FETs for once?  You can design a switch, phase shifter, attenuator, and vary FOM and see how the loss changes.  This is a nonlinear effect, the change is far more drastic raising FOM from 0.3 to 0.6 THz than it is raising from 0.6 to 0.9 THz.  the higher the FOM, the bigger fraction of loss is due to metal in the circuit, not the FETs... For a commercial GaAs process, FOM might be 0.3 THz, which partly explains why commercial MMIC switches are lossy.  For a good GaN process, FOM can be much higher, an extreme example is Northrop Grumman's SLCFET.
• The model includes "contact resistance" which is a component of the channel resistance in the on-state.  This also affects the off-state, an effect that is often ignored. The way RC is controlled it to pick a fraction of RON that is contained in each contact.  The default we chose is 33%, ask your favorite process nerd for a more accurate value.
• The model includes Roff.  Roff is never zero, but hopefully it is a high value.  We set it to 5000 ohms for a 1mm FET as the default.  The next time you have a switch FET on your curve tracer, zoom in at the pinch-off line, it is never horizontal, so Roff is never infinite.  GaN processes are often worse than GaAs processes in this regard. Leakage current increases switch loss.
• We included the intrinsic resistance of the gate-to-source and gate-to-drain contacts.  These have a small effect on off-state parameters as you will see.
• It is a three terminal model, with the gate resistance a function of the number of gate fingers.  The default value is 2 ohms for a 1mm gate, this means that if you measured the resistance across a 1mm gate you would see 4 ohms.  2 ohms is the average value, which is half of the end-to-end value.  Can you dig that or do you need a PowerPoint presentation?
• Speaking of RG, in an amplifier (an in particularly in an LNA) you would want to minimize it. In a switch, RG is your friend as it decouples the gate terminal from RF signals you want to control.  In a switch design the gate terminal is always connected to a mesa resistor of typically 5K ohms to really choke it off.
• Even though this is a three terminal model, you can delete terminal 3 (the gate terminal), or simply not connect it and be Switch Design Hero.  We left it in the model in case you want to evaluate leakage out the gate terminal, before you delete it and get on with your design.
• We set Coff to 0.25pF/mm.  This varies from process to process, in practice you will see maybe +/-20% beyond the value we chose.
• Coff is distributed between CDS and the two CG terms.  We allow you to pick the fraction of Coff that is associated with the gate terminal.  CG couples energy through the intrinsic resistance RI, which caused loss.
• The on-capacitance is always higher than the off capacitance.  We arbitrarily set it to 2xCoff.  But you will see it has almost no effect, because the Ron term shorts it out.

## Sensitivity analysis of the Microwaves101 switch FET model

Let's start with a simple circuit where we shunt the FET model across two ports, in two different states (off at port 1, on at port 2).  We set the periphery to 500um, the rest of the parameters are internally set according to the graphic above which coincidentally was set to 500um, with FOM=0.5 THz.  The graphic shows all of the individual lumped element values.

Below the FET model response is shown in both states, on the Smith chart so you can see how far from an open circuit the capacitance takes you in the off-state, and on a rectangular plot in dB so you can see how close the values are to ideal (zero dB). The on-state is boring, it is essentially the response of an xx ohm resistor (will get back to you on that after we update the graphic....). As we said, Con has no discernible effect on the response in the on-state.

What if the FET was a perfect RC circuit? That is plotted below on both Smith and dB magnitude plots. In the off state, the reflection coefficient is perfect 0 dB, on the Smith chart, you can barely tell the difference between ideal and the full model, unless you look close and see the full model is not a perfect gamma=unity situation and is getting worse with frequency.

Let's look at the individual contributions of RC, RI, and Roff. plotted in decibels only.  We don't have to tell you that RG has zero affect on performance, so long as the gate is decoupled with a large resistor, right?

Here below, Roff is 5000 ohms.  You will see it affects the reflection coefficient at all frequencies. It is not a big deal at 500 ohms, but you need to insist that your process people understand that when a decvice is pinched off, it really needs to be clse to ideal.  IN a power amplifier, no one cares if there is a few percent of eh saturated current left, but a switch designer should care.

OK, let's turn on RC: it has a much bigger effect, that gets worse with frequency. By the way, in all of these cases, this is real resistive loss, the kind you can't match out.

Finally, let's look at RI: it is similar to the effect of RC but in this case not as bad.

If you add up the effects of the previous three plots you get back to the full model, which we plotted at the beginning of this page. If you ignore the parasitic resistances and design a switch, you will miss your predicted loss.

## Example SPDT switch design

Coming soon!

Author : Unknown Editor