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MMIC Switch Design Example 2

Here's an example of a wideband 2xSPDTswitch. Starting with an image from Liam Devlin at Plextek, we've analyzed the circuit, much the way an unscrupulous competitor would when they begin a reverse-engineering job. Maybe later Liam can let us know how close we came.

The die photo below reveals quite a lot. The foundry that fabbed the part is TriQuint Texas, you can tell by the "TQS" designation. This is a series/shunt/shunt/shunt design. The "16 26" number on the lower left of the chip is a unique row/column number which is a good idea when you want to match up a particular chip with data that was measured on-wafer. This reminds us of a story from a long time ago...

When a certain GaAs fab was being set up, the production line copied a feature that was typical of digital silicon fabs of the time (early eighties) and put in place a die inking system. The intent was that data would be collected for each chip (at this point it was just DC, not RF) and a "bad" die would receive a shot of indelible red ink so that after the wafer was scribed the good die could be easily sorted out and packaged for shipment. Unfortunately this idea doesn't work for expensive analog electronics, where "bad" is merely a relative judgement. The first time a production wafer came out, all of the good (non-inked) dice were picked. Then an order came in for ten more pieces, without a big budget or schedule that would allow for starting a new wafer lot... and the first question was raised, how well do the chips with 9.9 volt breakdown perform compared to the ones with 10.0 volts? Followed by the question, what solvents can be used to remove the indelible red die witout "harming" the chips? (Answer: none!) Followed by two questions, what are the dielectric properties of hardened, indelible red ink, and how does the amplifier perform if it has a thick red dot of uncontrolled diameter and height of ink on top of it? You get the picture, there's probably not a compound semi fab out there that inks "bad die" at on-wafer test these days! So we're all stuck with unique chip numbers and managing huge databases of data. Rats!

This switch appears to be an effort to provide good isolation over a very wide band. We'll guess that the design spec was to achieve 40 dB isolation from DC to 18 GHz, with loss allowed to creep up to 2 dB at the high end of the frequency band. The two switches on the die are independently operable from DC pads labeled 3, 4, 11 and 12. It looks like the designer had in mind an alternative where the two switches can be thrown from just two DC connections, by wirebonding the pads together at the center of the chip (near the Plextek logo). Wirebonding on-chip is not an ideal method of making connections, we would have preferred a removeable air-bridge jumper.

The switch FETs are connected with source and drain airbridges, as opposed to meandered gates shown in this example. Quite a few metal choke resistors are used to try to keep the RF off of the gate bias lines (these are purple rectangles connected to the gold traces). The circuit if fully RF probeable (note the alignment arrows at the probe interfaces which are used to maximize repeatability of the contact point). However, probing a three-port circuit can be an expensive nightmare, you'll need a custom dual probe for the right side of the switch. Maybe that's why this die has no signs of scratches from any RF or DC probes!

The shunt FETs are grounded with single via holes to save GaAs area. None of the three shunt FETs are the same periphery, this is a design parameter that can be leveraged in order to optimize the bandwidth.

MMIC Switch Design Example 2

We can estimate some of the important dimensions if we have an accurate size reference. We'll guess that the via hole pads on the second and third shunt FETs are 150x150 microns, and the RF probe pads are 100x100um.

We can come up with the following estimates for the FET peripheries (note: we didn't really try very hard to scale these, just a ruler against the computer screen):

Series FET: 3x100um

1st shunt FET: 3x50um

2nd shunt FET: 5x75um

3rd shunt FET: 3x100um

RF probe pitch: 250 um

Overall die size: 1560 x 2760 (a real monster!) The die thickness is probably 100 microns.

OK, Liam, how'd we do?

 

Author : Unknown Editor

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