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SLCFET

Update April 2018: here's a long video where Dr. Rob Howell explains just about everything you could ask about SLCFET.  For serious switch hobbyists only!

 Northrop Grumman Microsystems' Seminar: Robert Howell, "SLCFET and RF Switch Device Technology

Updated February 2016: at the bottom of this page we provide the SLCFET patent

A paper published at Compound Semiconductor IC Symposium 2014 shows a new way to make switch FETs with much higher figure of merit:

"Low Loss, High Performance 1-18 GHz SPDT Based on the Novel Super-Lattice Castellated Field Effect Transistor (SLCFET)" by R.S. Howell et al (Northrop Grumman Electronic Systems). Here at Microwaves101, we rated this paper the highest of all that were presented at the CSICS. Why? Because it represents something entirely new, and it is something entirely useful.

From the abstract:

...18 GHz SPDT RF switches... Measured insertion loss of the SPDT at 10 GHz was 0.4 dB, with 35 dB of isolation and 23 dB of return loss, along with a measured linearity OIP3 value 62 dBm and a P0.1dB of 34 dBm.

This is a GaN HEMT process on 100um SiC substrate and has demonstrated a switch figure of merit [1/(2piRONCOFF)] of 1.2 THz, with RON=0.65 Ohm-mm and COFF=0.21 pFmm. You would be hard pressed to get a few hundred GHz out of other any other GaN fab's processes. 

SLCFET answers the question, what if switch FET people could design their own gate structure instead of using the amplifier gate that is available in a process? The requirements for switches are vastly different from amplifiers, yet this has been virtually ignored until now.

Let's compare amplifier FETs to switch FETs, in terms of what requirements they do NOT share, then you can get an understanding of how to re-think your switch process. No charge for this free advice, now get some IRAD money and make it happen.  Be sure to reference this page and credit "the Unknown Editor" for these observations, as well as Dr. Howell's 2014 CSIC Symposium paper.

 Attribute

Amplifier FET 

Switch FET 

 

Tee top

 

You want gate resistance as low as possible as you are feeding an RF signal through the gate. This is the reason for the tee top on a sub-micron gate. 

 

Having high gate resistance is actually a good thing, as you want to choke off the RF signal from exiting this terminal. A tee top increases off-capacitance. Get rid of it, it is going to kill millimeter-wave performance. 

 

Field plate

 

Used to reduce peak electric field across the channel, this invention was instrumental in making GaN power amplifier reliable

 

Get. Rid. Of. It. Field plates increase off-capacitance.

 

Metal thickness

 

In order to carry DC current you will want to maximize metal thickness

 

There is no DC current, and it takes quite a lot of RF power to create an ampere of RF current.  Non-essential thick metal increases off-capacitance; use minimum thickness.  You can even consider no plated metal on top or the source-drain metal (which is quite thin but has significantly lower conductivity than gold).

 

Gate-to-gate spacing 

 

Because of heat dissipation in close quarters there is a lower limit on gate-gate spacing (unless you believe that diamond heat sinks will someday magically solve this problem).

 

Ideally you could space the gates 10um pitch if you need big FET to shrink the FET footprint. You may have to obey some rules in the case that you need to land an air-bridge to tie sources (or drains) together. Increasing the gate spacing makes the FET physically larger, which adds more capacitance to ground which is a bad thing. In a shunt FET, capacitance to ground adds directly to COFF.

 

Gate length

 

Reduce it to get more gain

 

No need to reduce gate length, except in the context that you want to minimize the channel between the source and drain contacts

 

Substrate thickness Many fabs are using 50um thickness in order to allow individual source vias for power amps (which will increase FT and FMAX). For a switch, thinner substrates mean thinner interconnect transmission lines for the same impedance. This drives up metal loss.  For lowest loss, use the thickest substrate available... it would be great if some fabs introduced 150um thick substrates for X-band or lower frequency.

 

So what is the secret sauce of SLCFET? There are two actually.  First, it uses a super-lattice structure which can have multiple levels of 2D sheet charge to carry RF current at lower loss. The paper does not reveal how many layers of sheet charge are present, but with a little bit of thought you can surmise it is at least four to get the reported RON (let's say 1/2 the "normal" RON was achieved... and the process etched off 50% of the available channel to castellate the gate). The second feature is the castellated gate, which was necessary to pinch off all of those extra buried channels.  It the photo below we have attempted to recreate the gate structure using some  cheap cookies and Hershey's syrup, which plays favorably to today's television audience of fat people watching cooking shows. The cookies (keks if you work at Fraunhofer IAF) are on the order of 0.5 x 1.0 micron, the syrup is supposed to be 0.25 um but our e-beam needs calibration. Where the cookies are missing was etched off before the gates were processed. If you cut a cross section under the gates you would see castellations, similar to the crenellations that allowed some protection to archers on European castles, centuries ago. Why go to all the bother of castellating the gate? Super-lattice HEMTs have a habit of not pinching off, as the E-field under the gate does not penetrate down to the bottom of the epi-stack. Wrapping the gate around the mesa means that the E-field can penetrate from three directions, flushing all the charge out of the channels. From a DC perspective, the one thing you might notice is the relatively high pinch-off voltage, around -8 volts.

You might also want to consider that SLCFET is protected by patents before you try to clone it. See the SLCFET patent at the bottom of this page.

 

SLCFET dessert 800

SLCFET is the just dessert for MEMS switch engineers...

 

By the way, we threw that mess out, no one actually ate it.

Speaking of castles, below the French defend themselves from King Arthur. You can think of Arthur as a MEMS engineer looking for the Holy Grail of switch technologies, while the people in the castle are Northrop Grumman in Baltimore and they already have it...

 

 Bibliography

[1] R.S. Howell et al"Low Loss, High Performance 1-18 GHz SPDT Based on the Novel Super-Lattice Castellated Field Effect Transistor (SLCFET)" 2014 CSIC Symposium

[2] U.S. patent  9202906, Superlattice crenelated gate Field Effect Transistor

 

Author : Unknown Editor

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