# MMIC phase shifter 45 degree bit design

Click here to go to our main page on phase shifters

Go to our download page and get a copy of the MWO file that was used to generate content for this page.

**New for January 2024.** This is the fourth installment of an article on designing a four-bit phase shifter.

Click here to go to the first installment of a four-bit phase shifter design in MWO

Click here for the second installment of this article on phase shifter design, where we correct the RMS phase error calculation.

Click here for the third installment, where we design a MMIC 22-degree bit

Click here to go to the fifth installment, where we design a MMIC 90-degree bit

Click here to go to the sixth installment, where we design a MMIC SPDT switch used in a MMIC 180-degree bit

Click here to go to the seventh installment, where we design a MMIC 180-degree bit

Click here to go to the eighth installment, where we complete the four-bit MMIC phase shifter preliminary design

In the previous episode we created a preliminary MMIC 22-degree bit including layout. Now we will look at a 45-degree bit. Here is something you should know about phase shifter design. The Phase Shifter Gods have decided for mankind that the 45-degree bit is always the easiest bit design in a digital phase shifter! The 90- and 180-degree bits each have their struggles as you will see later.

The design file for this page is available on our download area. We made a bunch of improvements to the phase error calculations to make them less awkward, but we won't be going backwards and fixing the previous design files.

Here is our MMIC 45-degree bit schematic. It follows the Campbell-Brown architecture described on this page, with two FETs that are turned on and off opposite to each other. Q1 behaves like a series capacitor or a near-short circuit, Q2 is a shunt FET with a resonator that behaves (kind of) like a short or an open in its two states. Together they form a high-pass pi filter, and in the other state nearly a "through" connection.

In the 22-degree bit lesson we neglected a key point. Within a multi-bit design, each bit is controlled by variable "state" which will step from 0 to 15. We need to convert "state" to a value of "on" which will be either 0 or 1 to control the FETs. The state equation appears at the top of the schematic, which you probably can't read, so here it is enlarged:

Let's look at what the state equation does for the four bits. Wow, it creates 0 to 15 to a binary sequence! You should hire the guy that came up with that masterpiece.

bit | ||||

state | 0 | 1 | 2 | 3 |

0 | 0 | 0 | 0 | 0 |

1 | 1 | 0 | 0 | 0 |

2 | 0 | 1 | 0 | 0 |

3 | 1 | 1 | 0 | 0 |

4 | 0 | 0 | 1 | 0 |

5 | 1 | 0 | 1 | 0 |

6 | 0 | 1 | 1 | 0 |

7 | 1 | 1 | 1 | 0 |

8 | 0 | 0 | 0 | 1 |

9 | 1 | 0 | 0 | 1 |

10 | 0 | 1 | 0 | 1 |

11 | 1 | 1 | 0 | 1 |

12 | 0 | 0 | 1 | 1 |

13 | 1 | 0 | 1 | 1 |

14 | 0 | 1 | 1 | 1 |

15 | 1 | 1 | 1 | 1 |

Here is the "bit test" schematic for the 45-degree bit. We left the original lesson-one lumped element bit in there but disabled it, it might be worth a look at it again.

Here is the optimized 45-degree bit amplitude response in the two states. It has much better performance than the 22-degree bit. The loss of this design is phenomenal, at less than 0.5 dB in both states, but that's pretty optimistic. The main reason for the low loss is that we are using a switch FET with Figure of Merit of 400 GHz, which is much higher than most available GaAs and GaN processes. But it is not unheard of: a 2022 paper at CS Mantech by AFRL presented a 140nm GaN process with 600 GHz switch figure of merit. You can download the paper for free, here. If anyone is going to CS Mantech in 2024 (in Tucson), let's get together!

We've showed you the equation for calculating phase shift for a single bit back in lesson one. Here is the optimized phase response, it shows very low phase error.

Now, let's replace the FET models with T-lines of the same overall dimension so we can look at the layout.

Instead of just looking at just the 45-degree bit, we cascaded it with the 22-degree MMIC bit in our overall four-bit schematic, then generated a layout.

Here are the two bits laid out next to each other. Where are the gate control lines? You don't need to worry about them until the design is almost done.

Next up: the 90-degree MMIC bit!