# MMIC phase shifter 90 degree bit design

Click here to go to our main page on phase shifters

Go to our download page and get a copy of the MWO file that was used to generate content for this page.

**New for February 2024.** This is the fifth installment of an article on designing a four-bit phase shifter.

Click here to go to the first installment of a four-bit phase shifter design in MWO

Click here for the second installment of this article on phase shifter design, where we correct the RMS phase error calculation.

Click here for the third installment, where we design a MMIC 22-degree bit

Click here to go to the fourth installment, where we design a MMIC 45-degree bit

Click here to go to the sixth installment, where we design a MMIC SPDT switch used in a MMIC 180-degree bit

Click here to go to the seventh installment, where we design a MMIC 180-degree bit

Click here to go to the eighth installment, where we complete the four-bit MMIC phase shifter preliminary design

Like the 45-degree bit, we employed the Campbell-Brown topology switched filter topology for our 90-degree bit. This is always a stretch, you end up with much less bandwidth than you get for lower phase-shift bits. We would tell you a better way to do design a 90-degree bit, but then we would have to kill you so you don't try to copy it (JK!) Below is the 90-degree bit schemati. The design file for this page is located in our download area, grab a copy of you are using AWR/Microwave Office, then you will be able to read all of the dimensions.

We spent a few hours optimizing the results, while going back-and-forth with the layout to make sure the artwork is a work of art. Below is the layout result. Once again, we substituted two transmission lines for the FETs to generate the layout, and we are ignoring the resistor network for controlling them. This is a cartoon layout, there is no need to bog it down with details, and there is no need to do any EM analysis until we have a four-bit cartoon design.

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Using the "bit test" schematic (look at the 22 and 45 bit lessons), we generated the phase shift response below. Note that it is a compromise, and has a non-zero value at center frequency. Welcome to analog electronics, where beauty is in the eye of the beholder!

Here are the insertion losses and return losses of the two states. S11 and S21 represent the phase state (the series FET is capacitive) and S33 and S43 are the reference state (series FET is resistive). Once again, because of symmetry we are ignoring S22 and S44.

## Four-bit phase shifter simulation

Let's place the new 90-degree bit into the four-bit schematic. The 180 bit is still a an ideal switched, lumped-element filter. We are putting the bits in order from LSB to MSB, but there is no reason you can't mix them up if you want to try to improve the overall response (good luck with that!)

Let's look at amplitudes first. Here are the transmission losses of the sixteen states. We are on track to hit 2 dB loss for the overall phase shifter, but bear in mind we used a very sporty 400 GHz switch FET Figure of Merit. The 180-degree bit will dominate the loss, we expect up to 3 dB loss for the full design. The purple line is the average loss as calculated by Microwave Office. Technically, RMS amplitude value should be calculated from voltages, not decibels, but the error is small so we won't try to chase it down.

Below is the RMS amplitude error, as calculated by AWR/MWO.

Now let's look at the phase states. first, we plot them as AWR calculated them (the wrong way), such that the reference state is one of the actual phase states and other states are subtracted from it.

Below are the phase errors calculated from the AWR phase states. Note that they are not centered around Y=0.

Now let's look at the phase state calculated the correct way, where the reference state is calculated to minimize phase errors.

Let's look at the phase errors the M101 way. Wow, they sure look good compared to the AWR method!

Below we plotted the RMS phase errors using the two methods. Do yourself a "phaver" and always calculate the phase states the correct way.

Now we will look at the return losses. At this point we realize that we cannot maintain 10 dB across 9 to 11 GHz bandwidth, unless we add some attenuators on each side of the phase shifter to pad it down. Nah...there's no need to do that. Just do your best to match it.

Finally, let's look at our four-bit layout, which is still missing the 180-degree bit. The length or the chip so far is 1.85 mm, it will probably be 3mm long when we add the 180-degree bit. Phase shifters use up a lot of GaAs, but the alternative is to make them on silicon, and suffer 4X more loss and much lower linearity.

Next up: the 180-degree bit!

**Author : **Unknown Editor